Dram technology compatible processor/memory chips

ABSTRACT

The present invention includes a programmable logic array having a first logic plane that receives a number of input signals. The first logic plane has a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A number of non-volatile memory cells arranged in rows and columns of a second logic plane receive the outputs of the first logic plane and are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function. Each non-volatile memory cell includes a MOSFET. Each non-volatile memory cell includes a stacked capacitor formed according to a DRAM process. Each nonvolatile memory cell includes an electrical contact that couples the stacked capacitor to a gate of the MOSFET. The present invention also includes methods for producing the Ics and arrays.

[0001] This application is a Divisional of U.S. patent application Ser.No. 09/261,598, filed Feb. 26, 1999 which is incorporated herein.

RELATED APPLICATIONS

[0002] This application is related to commonly assigned applications,U.S. patent application Ser. No. 09/259,493, filed Feb. 26, 1999, nowU.S. Pat. No. 6,380,581, U.S. patent application Ser. No. 09/261,597,filed Feb. 26, 1999, now U.S. Pat. No.6,297,989, and U.S. patentapplication Ser. No. 09/261,479, filed Feb. 26, 1999, now U.S. Pat. No.6,256,225 which are hereby incorporated by reference.

FIELD OF THE INVENTION

[0003] The present invention relates generally to semiconductorintegrated circuits and, more particularly, to DRAM technologycompatible processor/memory chips.

BACKGROUND OF THE INVENTION

[0004] Many products need various amounts of memory. Two of the mostuseful types of memory are high speed, low cost memory typicallyimplemented as Dynamic Random Access Memory (DRAM) and non-volatilememory typically implemented as Electrically Erasable and ProgrammableRead Only Memory (EEPROM) or Flash memory. The ability to combine DRAMand EEPROM styles of memory, as well as logic and data processingfunctions implemented by Programmable Logic Arrays (PLA's) especially iflittle or no additional manufacturing complexity is required, wouldallow a number of cost effective applications that do not currentlyexist or that, heretofore were too costly to be commercially viable.

[0005] With the increasing array density of successive generations ofDRAM chips, the attractiveness of merging other functions onto the chipalso increases. However, any successful merged technology product mustbe cost competitive with the existing alternative of combining separatechips at the card or package level, each being produced withindependently optimized technologies. Any significant addition ofprocess steps to an existing DRAM technology in order to provide addedfunctions such as high speed logic, SRAM or EEPROM becomes rapidly costprohibitive due to the added process complexity cost and decreasedyield. Thus, there is a need for a means of providing additionalfunctions on a DRAM chip with little or no modification of the DRAMoptimized process flow.

[0006] Among the desired additional functions, EEPROM is one for whichthe differences between the separately optimized technologies is thegreatest. The typical EEPROM cell consists of a MOSFET with two stackedgates, a floating gate directly over the device channel and a controlgate atop and capacitively coupled to it.

[0007] It would be very desirable to reduce all the major elements of aPC on to a single chip, including CPU, memory and input/output. While atthe present time it may not be possible to make a whole PC on a singledie, many processor like functions might most conveniently be embeddedon the DRAM die. PLAs on a DRAM die would be well suited for memoryaddress correction/repair by changing the addresses to remove faultyrows/columns, and replace them with functional ones. An example of aredundancy repair scheme is shown in U.S. Pat. No. 5,324,681 issuedLowrey on Jun. 28, 1994. Another is provided in U.S. Pat. No. 4,051,354issued Choate on Sep. 27, 1997. Another is provide in U.S. Pat. No.5,327,380 issued Kersh III on Jul. 5, 1994. None of these, however,incorporate an optimized DRAM technology process flow. PLAs on a DRAMdie would also be desirable for use as dedicated processors embedded onthe DRAM chip.

[0008] Recent publications outline the problems in trying to embed DRAMsin high performance ULSI logic. The conclusions are that because of theheight differences between conventional stacked capacitor DRAM cells andhigh performance logic circuits that this can only be reasonablyaccomplished with trench capacitor DRAMS.

[0009] Modem DRAM technologies are driven by market forces andtechnology limitations to converge upon a high degree of commonality inbasic cell structure. For the DRAM technology generations from 4 Mbitthrough 1 Gbit, the cell technology has converged into two basicstructural alternatives; trench capacitor and stacked capacitor. Amethod for utilizing a trench DRAM capacitor technology to provide acompatible EEPROM cell has been described in U.S. Pat. No. 5,598,367. Adifferent approach is needed for stacked capacitors however.

[0010] Thus, there is a need for merging processor and memory functionson a single DRAM chip. Similarly, there is a need for using PLAs on aDRAM chip as decoder devices. It is desirable that such processor/PLAcapability be fabricated onto the DRAM chip with little or nomodification of the DRAM optimized process flow.

SUMMARY OF THE INVENTION

[0011] The above mentioned problems for merging processor/PLAs andmemory functions on a single DRAM chip as well as other problems areaddressed by the present invention and will be understood by reading andstudying the following specification. The present invention includes acompact non-volatile memory cell structure formed using a DRAM processtechnology.

[0012] The present invention includes a programmable logic array havinga first logic plane that receives a number of input signals. The firstlogic plane has a plurality of non-volatile memory cells arranged inrows and columns that are interconnected to provide a number of logicaloutputs. A second logic plane is provided which has a number ofnon-volatile memory cells arranged in rows and columns that receive theoutputs of the first logic plane and that are interconnected to producea number of logical outputs such that the programmable logic arrayimplements a logical function. Each non-volatile memory cell includes ametal oxide semiconductor field effect transistor (MOSFET). Eachnon-volatile memory cell includes a stacked capacitor formed accordingto a dynamic random access memory (DRAM) process. And, each non-volatilememory cell includes an electrical contact that couples the stackedcapacitor to a gate of the MOSFET.

[0013] Another embodiment of the present invention includes an addressdecoder for a memory device. The address decoder includes a number ofaddress lines and a number of output lines. The address lines, and theoutput lines form an array. A number of non-volatile memory cells aredisposed at intersections of output lines and address lines. Eachnon-volatile memory cell includes a metal oxide semiconductor fieldeffect transistor (MOSFET), a stacked capacitor formed according to adynamic random access memory (DRAM) process, and an electrical contactthat couples the stacked capacitor to a gate of the MOSFET. Thenonvolatile memory cells are selectively programmed such that thenon-volatile memory cells implement a logic function that selects anoutput line responsive to an address provided to the address lines.

[0014] These and other embodiments, aspects, advantages, and features ofthe present invention will be set forth in part in the description whichfollows, and in part will become apparent to those skilled in the art byreference to the following description of the invention and referenceddrawings or by practice of the invention. The aspects, advantages, andfeatures of the invention are realized and attained by means of theinstrumentalities, procedures, and combinations particularly pointed outin the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1 is a perspective view illustrating in detail the make up ofeach nonvolatile memory cell according to the teachings of the presentinvention.

[0016]FIG. 2 is a simplified block diagram of a field programmable logicarray (PLA) according to the teachings of the present invention.

[0017]FIG. 3 is a schematic diagram illustrating generally anarchitecture of one embodiment of a programmable logic array (PLA)constructed according to the teachings of the present invention.

[0018]FIG. 4 is a schematic diagram illustrating generally anarchitecture of one embodiment of a programmable decoder according tothe teachings of the present invention.

[0019]FIG. 5 illustrates application of programmed logic arrays (PLA's),formed according to the teaching of the present invention, embeddedprocessor on a DRAM die.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] In the following detailed description of the invention, referenceis made to the accompanying drawings which form a part hereof, and inwhich is shown, by way of illustration, specific embodiments in whichthe invention may be practiced. In the drawings, like numerals describesubstantially similar components throughout the several views. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention. Other embodiments may be utilizedand structural, logical, and electrical changes may be made withoutdeparting from the scope of the present invention. The terms wafer andsubstrate used in the following description include any structure havingan exposed surface with which to form the integrated circuit (IC)structure of the invention. The term substrate is understood to includesemiconductor wafers. The term substrate is also used to refer tosemiconductor structures during processing, and may include other layersthat have been fabricated thereupon. Both wafer and substrate includedoped and undoped semiconductors, epitaxial semiconductor layerssupported by a base semiconductor or insulator, as well as othersemiconductor structures well known to one skilled in the art. The termconductor is understood to include semiconductors, and the terminsulator is defined to include any material that is less electricallyconductive than the materials referred to as conductors. The followingdetailed description is, therefore, not to be taken in a limiting sense,and the scope of the present invention is defined only by the appendedclaims, along with the full scope of equivalents to which such claimsare entitled.

[0021]FIG. 1 is a perspective view illustrating in detail the make up ofthe nonvolatile memory cell, e.g. 100, according to the teachings of thepresent invention. The non-volatile memory cell 100 includes all theembodiments of the non-volatile memory cell structure presented anddescribed in detail in the co-filed application attorney docket number303.556us1, entitled “DRAM Technology Compatible Non-volatile MemoryCells,” by Wendell P. Noble and Eugene H. Cloud, which is herebyincorporated by reference in its entirety.

[0022] As shown in FIG. 1, the non-volatile memory cell structure 100includes a MOSFET 110 and a capacitor 120 fabricated using conventionalDRAM process steps. In one embodiment, the MOSFET 110 includes ann-channel metal oxide semiconductor (NMOS) transistor 110 formed in asemiconducting substrate 111. The MOSFET 110 includes a gate 112separated by a gate oxide 113 from a channel region 114 of the MOSFET110. In one embodiment, the gate oxide 113 has a thickness of less than100 Angstroms (Å) and acts as a tunneling oxide. Gate 112 includes apolysilicon gate 112, a polycide gate 112, salicided gate structure, orother conductive gate material as known to one of ordinary skill in theart of DRAM transistor fabrication. The channel region 114 couples afirst diffused region 115 to a second diffused region 116. The DRAMtransistor is formed according to a conventional, DRAM optimized processflow, as is known to those of ordinary skill in the art of DRAM chipfabrication.

[0023] As shown in FIG. 1, the capacitor 120 is formed in a subsequentlayer above the MOSFET 110. The capacitor 120 is separated from theMOSFET 110 by an insulator layer 132. Capacitor 120 includes a bottomplate 121 and a top plate 123, or a control gate 123 which is separatedfrom the bottom plate 121 by a dielectric layer or capacitor dielectric122. The bottom plate 121 serves as a storage node 121 and the top plateserves as a plate capacitor 123 for the capacitor 120. The bottom plate121 comprises a floating gate 121 for the non-volatile memory cell 100which is connected through insulator layer 132 to gate 112 by anelectrical contact 130. In one embodiment, the entire stack 121, 130 and112 serves as a floating gate. The top plate 123 comprises a controlgate 123 for the non-volatile memory cell 100.

[0024] In one embodiment, shown in FIG. 1, capacitor 120 includes astacked capacitor which is cup shaped 120. The bottom plate 121 hasinterior walls 121A and exterior walls 121B. The capacitor dielectric122 is conformal to the interior walls 121A and the exterior walls 121Bof the bottom plate 121. The top plate 123 is conformal to the capacitordielectric 122. A portion of the top plate 123 is located within andopposes the interior walls 121A of the bottom plate 121, separatedtherefrom by the capacitor dielectric 122. A portion of the top plate123 is locate outside of and opposes the exterior walls 121B of thebottom plate 121, separated therefrom by the capacitor dielectric 122.In one embodiment, the capacitor dielectric has a thickness of less thanthe equivalent of 100 Angstroms (Å) of SiO₂. As one of ordinary skill inthe art will understand upon reading this disclosure, other of stackedcapacitor 120 configurations, such as domes or flat plates, areapplicable. To create an array of such cells, such as shown in theco-filed application attorney docket number 303.556us1, entitled “DRAMTechnology Compatible Non-volatile Memory Cells,” by Wendell P. Nobleand Eugene H. Cloud, bit lines are connected to the first and seconddiffused regions, 115 and 116. For minimum cell size, the bit lines mayconsist of diffusion lines which traverse the array. By then patterningthe top plate 123 of the stacked capacitor 120 into strips orthogonal tothe diffused bit lines, control gate 123 word lines couple to the bottomplate 121 and the MOSFET 110 of the non-volatile memory cell 100structure.

[0025] The resulting non-volatile memory cell 100 has the same physicaland electrical features as conventional non-volatile memory cells andthus conventional methods of programming (e.g. channel hot electron“CHE” injection) and erasure (e.g. Fowler Nordheim “F-N” tunneling) maybe used. However, whereas conventional non-volatile memory cells havecapacitive coupling ratios of 0.6 to 1.0, as defined in the co-filedapplication attorney docket number 303.556us1, entitled “DRAM TechnologyCompatible Non-volatile Memory Cells,” by Wendell P. Noble and Eugene H.Cloud, the inherently high stacked capacitor 120 surface area of thepresent invention can provide coupling ratios many times this. Thereforethe gate voltage swings needed for programming and erasure are greatlyreduced.

[0026]FIG. 2 is a simplified block diagram of a field programmable logicarray (PLA) 200 according to the teachings of the present invention. PLA200 includes two major constituents: a first logic plane 220 and asecond logic plane 230. The first and second logic planes 220 and 230are formed using an array of non-volatile memory cells 100 as presentedand described in detail in connection to FIG. 1. In one embodiment, thefirst and second logic planes 220 and 230 each comprise NOR logiccircuits such that PLA 200 implements NOR-NOR logic. In otherembodiments, first and second logic planes 220 and 230 are constructedfrom arrays of non-volatile memory cells 100 that are configured toimplement AND-OR, OR-AND, NAND-NAND, NOR-OR, OR-NOR, AND-NOR, andNAND-AND logic.

[0027] Input lines 225 are coupled to receive a number of input signals.Inverters/drivers 250 are coupled to the input lines 225 such that firstlogic plane 220 is capable of receiving each of the input signals andtheir complements. First logic plane 220 produces a number of outputsignals that are logical combinations of the signals frominverters/drivers 250. The output signals from first logic plane 220 areprovided to second logic plane 230 via interconnection lines 222. Secondlogic plane 230 produces a number of output signals that are logicalcombinations of the signals from interconnection lines 222.

[0028] In addition, various control circuits and signals not detailedherein initiate and synchronize the PLA 200 operation as known to thoseskilled in the art. The PLA 200 implementation described with respect toFIG. 2 is illustrative only and is not intended to be exclusive orlimiting.

[0029]FIG. 3 is a schematic diagram illustrating generally anarchitecture of one embodiment of a programmable logic array (PLA),indicated generally at 300, and constructed according to the teachingsof the present invention. PLA 300 implements an illustrative logicalfunction using a two level logic approach. Specifically, PLA 300includes first and second logic planes 310 and 320. In this example, thelogic function is implemented using NOR-NOR logic. First and secondlogic planes 310 and 320 each include an array of non-volatile memorycells 100, as presented and described in detail in connection to FIG. 1,that are configured to implement the logical function of PLA 300.

[0030] It is noted that the configuration of FIG. 3 is provided by wayof example and not by way of limitation. Specifically, the teachings ofthe present application are not limited to programmable logic arrays inthe NOR-NOR approach. Further, the teachings of the present applicationare not limited to the specific logical function shown in FIG. 3. Otherlogical functions can be implemented in a programmable logic array withnon-volatile memory cells 100 using any one of the various two levellogic approaches.

[0031] First logic plane 310 receives a number of input signals at inputlines 312. In this example, no inverters are provided for generatingcomplements of the input signals. However, first logic plane 310 caninclude inverters to produce the complementary signals when needed in aspecific application.

[0032] First logic plane 310 includes a number of non-volatile memorycells 100 that form an array. The non-volatile memory cells 100 arelocated at the intersection of input lines 312, and interconnect lines314. Not all of the nonvolatile memory cells 100 are operativelyconductive in the first logic plane. Rather, the non-volatile memorycells 100 are selectively programmed to respond to the input lines 312and change the potential of the interconnect lines 314 so as toimplement a desired logic function. Thus, some non-volatile memory cells100 are left unprogrammed. This selective interconnection is referred toas programming since the logical function implemented by theprogrammable logic array is enterred into the array by the non-volatilememory cells 100 that are used at the intersections of input lines 312,and interconnect lines 314 in the array.

[0033] In this embodiment, each of the interconnect lines 314 acts as aNOR gate for the input lines 312 that are connected to the interconnectlines 314 through the non-volatile memory cells 100 of the array. Forexample, interconnection line 314 a acts as a NOR gate for the signalson input lines 312 a, 312 b and 312 c. That is, interconnect line 314 ais maintained at a high potential unless one or more of the non-volatilememory cells 100 that are coupled to interconnect line 314 a are turnedon by a high logic level signal on one of the input line 312. When acontrol gate address is activated, through input lines 312, eachnon-volatile memory cell 100 either conducts or does not conductdepending on the charge stored upon its floating gate, this performs theNOR positive logic circuit function, an inversion of the OR circuitfunction results from inversion of data onto the interconnect lines 314through the non-volatile memory cells 100 of the array. The senseamplifiers 316 at the ends of the interconnect lines 314 are used asamplifiers and drivers for the passing data into the second array 320.In this manner a NOR-NOR is most easily implemented utilizing the normalDRAM array structure, only the function of devices is changed.

[0034] In a similar manner, second logic plane 320 comprises a secondarray of non-volatile memory cells 100 that are selectively programmedto provide the second level of the two level logic needed to implement aspecific logical function. In this embodiment, the array of non-volatilememory cells 100 is also configured such that the output lines 318comprise a logical NOR function of the signals from the interconnectionlines 314 that are coupled to particular output lines through thenon-volatile memory cells 100 of the second logic plane 320.

[0035]FIG. 4 is a schematic diagram that illustrates one embodiment of adecoder, indicated generally at 400, that is constructed according tothe teachings of the present invention. Decoder 400 can be used, forexample, as a memory address decoder such as a column decoder or a rowdecoder.

[0036] Decoder 400 of FIG. 4 includes a number of non-volatile memorycells, e.g. 435, as described in detail in connection with FIG. 1. Thenumber of nonvolatile memory cells are formed at the intersection ofoutput lines O₁ through O₄ with either an address line A₁ through A₃ orinverse address line A₁ through A₃. The inverse address lines arecoupled to associated address lines through an inverter as shown. Forexample, non-volatile memory cell is located at the intersection ofaddress line A₁ and output line O₁. Decoder 400 is programmed andreprogrammed according to the techniques generally know for programmingconventional non-volatile memory cells. Any selected number of thenon-volatile memory cells be operatively coupled to the address lines,A₁ through A₃, inverse address lines, A₁ through A₃, or the outputlines, O₁ through O₄. In this manner, the number of non-volatile memorycells are selectively programmed into the array in order to implement adesired logical function.

[0037] In this embodiment of FIG. 4, each of the output lines, O₁through O₄, implements a NOR logic function for the address lines, A₁through A₃, and inverse address lines, A₁ through A₃, that are connectedto it through the vertical transistors. For example, output line O₁ iscoupled to the drains of non-volatile memory cells 435, 436, and 437.Non-volatile memory cells 435, 436, and 437 have gates, as shown indetail in FIG. 1, that are coupled to receive signals from address linesA₁, A₂, and A₃, respectively. Output line O₁ produces the logical NOR ofthe logic values provided on address lines A₁, A₂, and A₃. Output lineO₁ produces a low logic level when any one of the address lines A₁, A₂,and A₃ is brought to a high logic level and the floating gate on anassociated non-volatile memory cell, as shown in detail in FIG. 1, isabsent of charge (e.g. in an unprogrammed state). Further, output lineO₁ produces a high logic level only when the address lines A₁, A₂, andA₃ are all at a low logic level.

[0038] The remaining output lines are selectively coupled to othernon-volatile memory cells as shown to implement additional NORfunctions. These NOR functions are chosen such that the input addresslines, A₁, A₂, and A₃, (and inverse address lines, A₁, A₂, A₃) can beused to selectively address the output lines, O₁through O₄. It is notedthat the logical functions implemented in array 400 are shown by way ofillustration and not by way of limitation. Other logical functions canbe implemented without departing from the spirit and scope of thepresent invention.

[0039] Generally speaking, decoder 400 can be fabricated with N addressinput lines to uniquely select 2^(N) output lines. Thus, in analternative embodiment, two address lines, A₁ and A₂, are used toselectively access four output lines, O₁ through O₄. In this embodiment,the purpose of address line A₃ is to hold the output lines at a lowlevel when an address signal has not yet been received.

[0040]FIG. 5 illustrates application of PLA's, structure according tothe teachings of the present invention, as an embedded processor on aDRAM die 500. In the embodiment shown in FIG. 5, data from the DRAMmemory arrays 510 is input to the processor 520 at the top of the FIG. 5via interconnect lines 512. At the end of the processing, as defined bythe program selected for data processing from the program circuit 540,processed data is sent back for storage in the DRAM arrays 510 from adata output circuit 530 via interconnect lines 514. In one embodiment ofFIG. 5, the individual cell type for implementation of a particularprocessor 520 function includes a program stored in the program circuit540 using EEPROM cells. Memory is held in the memory arrays 510 andregisters 590 using conventional DRAM cells. In this embodiment, theindividual cell type for implementation of the particular processor 520function includes a function and sequence circuit 550, FLAGS 560, one ormore serial adders 570, and a data selector 580 using PLAs constructedaccording to teachings of the present invention. As is shown in FIG. 5,most functions in the processor can be implemented using PLA's accordingto the teachings of the present invention.

Conclusion

[0041] Thus, the ability to provide processor/PLA capability on a DRAMchip according to a DRAM optimized process flow has been shown by thepresent invention. This disclosure provides not only a technique forcombining logic (implemented with PLA's) with stacked capacitor DRAMcells but also describes the alternative approach to improving systemperformance, namely “embedded logic in DRAMs”, not DRAMs embedded inlogic.

[0042] The ability to process data stored on the DRAM die allows anumber of cost effective applications that do not currently exist orthat, heretofore were to costly to be commercially viable. It isparticularly suited to processing data which requires a large number ofparallel operations. The use of programmable embedded processors avoidsthe necessity of transferring intermediate data on and off chip throughinput/output drivers and circuits and greatly speeds data processing.This aids in applications such as a dedicated signal processor in whichdata may be loaded in to a range of DRAM addresses and then having analgorithm such as the Fast Fourier Transform (FFT), performed on thedata with the results stored in another range of DRAM memory all on thesame chip. The user application can retrieve the resultant processeddata from the memory. The ability of an on chip non-volatile memorymeans that the processor program instructions, implementing variousalgorithms, can not only be stored on the die but also can be easilychanged to suit a variety of applications. The PLA's of the presentinvention allow powerful techniques for data processing which areespecially useful for parallel data processing applications such asimage processing or general Digital Signal Processing (DSP). The PLA'sof the present invention are also suitable for making general purposeprocessors embedded in a DRAM by which one could emulate a generalpurpose processor such as an 80C251, an 8 bit general purposemicroprocessor. Here, 5-10 Mbits of the DRAM of the DRAM chip can beconfigured for PLA's, non-volatile storage, and where DRAM serves asregisters.

[0043] Thus, the ability to provide processor/PLA capability on a DRAMchip according to a DRAM optimized process flow has been shown by thepresent invention. This disclosure provides not only a technique forcombining logic (implemented with PLA's) with stacked capacitor DRAMcells but also describes the alternative approach to improving systemperformance, namely “embedded logic in DRAMs”, not DRAMs embedded inlogic.

[0044] The present invention includes a programmable logic array havinga first logic plane that receives a number of input signals. The firstlogic plane has a plurality of non-volatile memory cells arranged inrows and columns that are interconnected to provide a number of logicaloutputs. A second logic plane is provided which has a number ofnon-volatile memory cells arranged in rows and columns that receive theoutputs of the first logic plane and that are interconnected to producea number of logical outputs such that the programmable logic arrayimplements a logical function. Each non-volatile memory cell includes ametal oxide semiconductor field effect transistor (MOSFET). Eachnon-volatile memory cell includes a stacked capacitor formed accordingto a dynamic random access memory (DRAM) process. And, each non-volatilememory cell includes an electrical contact that couples the stackedcapacitor to a gate of the MOSFET.

[0045] Another embodiment of the present invention includes an addressdecoder for a memory device. The address decoder includes a number ofaddress lines and a number of output lines. The address lines, and theoutput lines form an array. A number of non-volatile memory cells aredisposed at intersections of output lines and address lines. Eachnon-volatile memory cell includes a metal oxide semiconductor fieldeffect transistor (MOSFET), a stacked capacitor formed according to adynamic random access memory (DRAM) process, and an electrical contactthat couples the stacked capacitor to a gate of the MOSFET. Thenonvolatile memory cells are selectively programmed such that thenon-volatile memory cells implement a logic function that selects anoutput line responsive to an address provided to the address lines.

[0046] Methods, integrated circuits, and electronic systems aresimilarly provided and included within the scope of the presentinvention.

[0047] It is to be understood that the above description is intended tobe illustrative, and not restrictive. Many other embodiments will beapparent to those of skill in the art upon reviewing the abovedescription. The scope of the invention should, therefore, be determinedwith reference to the appended claims, along with the full scope ofequivalents to which such claims are entitled.

What is claimed is:
 1. A method for forming a DRAM/EEPROM chip,comprising: forming a plurality of dynamic random access memory (DRAM)access transistors on a semiconductor substrate; forming a plurality ofstacked capacitors in a subsequent level above the plurality of DRAMaccess transistors and separated from the plurality of DRAM accesstransistors by an insulator layer; and coupling a first group of theplurality of stacked capacitors to a gate for each DRAM accesstransistor in a first group of the plurality of DRAM access transistors;coupling a second group of the plurality of stacked capacitors to adiffused region in a second group of the plurality of DRAM accesstransistors.
 2. The method of claim 1, wherein forming a plurality ofDRAM access transistors includes forming a plurality of n-channel metaloxide semiconductor (NMOS) transistors.
 3. The method of claim 1,wherein forming a plurality of stacked capacitors includes forming aplurality of stacked capacitors having a bottom plate, a capacitordielectric, and a top plate, wherein the bottom plate is formed in a cupshape having interior walls, the capacitor dielectric is formedconformal to the bottom plate and the top plate is formed conformal tothe capacitor dielectric, and wherein forming the plurality of stackedcapacitors includes forming a portion of the top plate within theinterior walls of the bottom plate.
 4. The method of claim 3, whereincoupling a first group of the plurality of stacked capacitors to a gatein each DRAM access transistors in a first group of the plurality ofDRAM access transistors includes coupling the bottom plate of eachstacked capacitor in the first group of the plurality of stackedcapacitors to the gate for the first group of the plurality of DRAMaccess transistors.
 5. The method of claim 1, wherein the forming aplurality of stacked capacitors includes forming the plurality ofstacked capacitors according to a dynamic random access memory (DRAM)process flow.
 6. A programmable logic array, comprising: a first logicplane that receives a number of input signals, the first logic planehaving a plurality of non-volatile memory cells arranged in rows andcolumns that are interconnected to provide a number of logical outputs;a second logic plane having a number of non-volatile memory cellsarranged in rows and columns that receive the outputs of the first logicplane and that are interconnected to produce a number of logical outputssuch that the programmable logic array implements a logical function;and wherein the non-volatile memory cells each include: a metal oxidesemiconductor field effect transistor (MOSFET); a stacked capacitorformed according to a dynamic random access memory (DRAM) process; andan electrical contact that couples the stacked capacitor to a gate ofthe MOSFET.
 7. The programmable logic array of claim 6, wherein thefirst logic plane and the second logic plane each comprise NOR planes.8. The programmable logic array of claim 6, wherein the substrate is abulk semiconductor.
 9. The programmable logic array of claim 6, whereinthe electrical contact includes a polysilicon plug.
 10. The programmablelogic array of claim 6, wherein the working surface of the substrateincludes an insulating layer formed on top of an underlyingsemiconductor.
 11. The programmable logic array of claim 6, wherein theprogrammable logic array is operatively coupled to a computer system.12. The programmable logic array of claim 6, wherein the stackedcapacitor includes a fin type capacitor.
 13. The programmable logicarray of claim 6, wherein the stacked capacitor includes a storage node,a capacitor dielectric, and a plate conductor and wherein the electricalcontact couples the storage node of the stacked capacitor to the gate ofthe MOSFET.
 14. An address decoder for a memory device, the addressdecoder comprising: a number of address lines; a number of output lines;wherein the address lines, and the output lines form an array; a numberof non-volatile memory cells that are disposed at intersections ofoutput lines and address lines, wherein each non-volatile memory cellincludes a metal oxide semiconductor field effect transistor (MOSFET), astacked capacitor formed according to a dynamic random access memory(DRAM) process, and an electrical contact that couples the stackedcapacitor to a gate of the MOSFET; and wherein the non-volatile memorycells are selectively programmed such that the non-volatile memory cellsimplement a logic function that selects an output line responsive to anaddress provided to the address lines.
 15. The address decoder of claim14, wherein the number of address lines includes a number ofcomplementary address lines that are disposed in the array.
 16. Theaddress decoder of claim 14, wherein the decoder is operatively coupledto a dynamic random access memory (DRAM) device.
 17. The address decoderof claim 14, wherein the array includes N address lines and 2^(N) outputlines.
 18. The address decoder of claim 14, wherein the number ofaddress lines includes a number of complementary address lines that areeach coupled to one of the address lines through an inverter and aredisposed in the array.
 19. An electronic system, comprising: a memory;and a processor coupled to the memory and formed on a die common withthe memory; and wherein the processor includes at least one programmablelogic array including: a first logic plane that receives a number ofinput signals, the first logic plane having a plurality of non-volatilememory cells arranged in rows and columns that are interconnected toprovide a number of logical outputs, and wherein the non-volatile memorycells each include: a metal oxide semiconductor field effect transistor(MOSFET); a stacked capacitor formed according to a dynamic randomaccess memory (DRAM) process; and an electrical contact that couples thestacked capacitor to a gate of the MOSFET.
 20. The electronic system ofclaim 19, wherein the programmable logic array includes a second logicplane having a number of non-volatile memory cells arranged in rows andcolumns that receive the outputs of the first logic plane and that areinterconnected to produce a number of logical outputs such that theprogrammable logic array implements a logical function.
 21. Theelectronic system of claim 20, wherein the first logic plane and thesecond logic plane each comprise NOR planes.
 22. The electronic systemof claim 19, wherein: the processor includes at least one registerformed from dynamic random access memory cells; and wherein theprocessor includes at least one function and sequence circuit.
 23. Theelectronic system of claim 19, wherein the processor includes a programcircuit that stores a program.
 24. The electronic system of claim 23,wherein the program circuit stores the program in an EEPROM.
 25. Anintegrated circuit formed in and on a semiconductor layer, theintegrated circuit comprising: a plurality of metal oxide semiconductorfield effect transistors (MOSFETs) formed in and on the semiconductorlayer; a plurality of stacked capacitors disposed above the plurality ofMOSFETs and separated from the plurality of MOSFETs by an insulatorlayer; and wherein a first group of the plurality of stacked capacitorsis selectively coupled to gates of the MOSFETs to form non-volatilememory cells for a first sub-circuit; wherein a second group of theplurality of stacked capacitors is selectively coupled to diffusedregions of the MOSFETs to form a second sub-circuit; and wherein thefirst sub-circuit is operatively coupled to the second sub-circuit. 26.The integrated circuit of claim 25, wherein the plurality of stackedcapacitors includes a plurality of stacked capacitors formed accordingto a dynamic random access memory (DRAM) process flow.
 27. An integratedcircuit, comprising: a processor; a memory, operatively coupled to theprocessor; and wherein the processor and the memory are formed on thesame semiconductor substrate and the processor includes at least oneprogrammable logic array with a non-volatile memory cell that includes ametal oxide semiconductor field effect transistor with a stackedcapacitor coupled to its gate.
 28. A method for forming an integratedcircuit, the method comprising: forming a plurality of metal oxidesemiconductor transistors (MOSFETs) in and on a layer of semiconductormaterial; forming a first set of stacked capacitors that are coupled todiffusion regions of selected ones of the plurality of MOSFETs to form amemory array; and forming, on the same layer of semiconductor material,a second set of stacked capacitors that are coupled to gates of selectedones of the plurality of MOSFETs to form a plurality of non-volatilememory cells; and interconnecting the memory array and the non-volatilememory cells to provide the integrated circuit.
 29. The method of claim28, wherein forming a second set of stacked capacitors comprises forminga second set of stacked capacitors that are coupled to gates of selectedones of the plurality of MOSFETs to form a EEPROM.
 30. The method ofclaim 28, wherein forming a second set of stacked capacitors comprisesforming a second set of stacked capacitors that are coupled to gates ofselected ones of the plurality of MOSFETs to form at least oneprogrammable logic array.
 31. The method of claim 28, wherein forming asecond set of stacked capacitors comprises forming a second set ofstacked capacitors that are coupled to gates of selected ones of theplurality of MOSFETs to form a memory decode array.
 32. The method ofclaim 28, wherein forming a second set of stacked capacitors comprisesforming a second set of stacked capacitors that are coupled to gates ofselected ones of the plurality of MOSFETs to form at least oneprogrammable logic array of a processor circuit.
 33. A programmablelogic array, comprising: a first logic plane that receives a number ofinput signals, the first logic plane having a plurality of non-volatilememory cells arranged in rows and columns that are interconnected toprovide a number of logical outputs; and a second logic plane having anumber of non-volatile memory cells arranged in rows and columns thatreceive the outputs of the first logic plane and that are interconnectedto produce a number of logical outputs such that the programmable logicarray implements a logical function, wherein the non-volatile memorycells each include: a transistor; a stacked capacitor formed accordingto a dynamic random access memory process, the capacitor providing acoupling ratio greater than 1.0; and an electrical contact that couplesthe stacked capacitor to a gate of the transistor.
 34. The programmablelogic array of claim 33, wherein the implemented logical functionincludes at least one of NOR-NOR, AND-OR, OR-AND, NAND-NAND, NOR-OR,OR-NOR, AND-NOR, and NAND-AND.
 35. The programmable logic array of claim33, wherein the first logic plane includes inverters adapted to generatecomplements of the input signals.
 36. The programmable logic array ofclaim 33, wherein the electrical contact includes a polysilicon plug.37. The programmable logic array of claim 33, wherein the stackedcapacitor includes a fin type capacitor.
 38. The programmable logicarray of claim 33, wherein the stacked capacitor includes a storagenode, a capacitor dielectric, and a plate conductor and wherein theelectrical contact couples the storage node of the stacked capacitor tothe gate of the transistor.
 39. The programmable logic array of claim33, wherein the transistor is a metal oxide semiconductor field effecttransistor.
 40. A programmable logic array, comprising: a first logicplane that receives a number of input signals, the first logic planehaving a plurality of non-volatile memory cells arranged in rows andcolumns that are interconnected to provide a number of logical outputs;and a second logic plane having a number of non-volatile memory cellsarranged in rows and columns that receive the outputs of the first logicplane and that are interconnected to produce a number of logical outputssuch that the programmable logic array implements a logical function,wherein the non-volatile memory cells each include: a metal oxidesemiconductor field effect transistor; a cup-shaped stacked capacitorformed according to a dynamic random access memory process, thecapacitor providing a coupling ratio greater than 1.0; and an electricalcontact that couples the stacked capacitor to a gate of the transistor.41. The programmable logic array of claim 40, wherein the implementedlogical function includes at least one of NOR-NOR, AND-OR, OR-AND,NAND-NAND, NOR-OR, OR-NOR, AND-NOR, and NAND-AND.
 42. The programmablelogic array of claim 40, wherein the first logic plane includesinverters that are adapted to generate complements of the input signals.43. The programmable logic array of claim 40, wherein the electricalcontact includes a polysilicon plug.
 44. The programmable logic array ofclaim 40, wherein the cup-shaped stacked capacitor includes a storagenode, a capacitor dielectric, and a plate conductor and wherein theelectrical contact couples the storage node of the stacked capacitor tothe gate of the transistor.
 45. A programmable logic array, comprising:a first logic plane that receives a number of input signals, the firstlogic plane having a plurality of non-volatile memory cells arranged inrows and columns that are interconnected to provide a number of logicaloutputs; and a second logic plane having a number of non-volatile memorycells arranged in rows and columns that receive the outputs of the firstlogic plane and that are interconnected to produce a number of logicaloutputs such that the programmable logic array implements a logicalfunction, wherein the non-volatile memory cells each include: a metaloxide semiconductor field effect transistor comprising a gate and achannel region separated by a gate oxide; a stacked capacitor formedaccording to a dynamic random access memory process, the capacitorproviding a coupling ratio greater than 1.0; and an electrical contactthat couples the stacked capacitor to a gate of the transistor.
 46. Theprogrammable logic array of claim 45, wherein the gate oxide has athickness of less than 100 angstroms.
 47. The programmable logic arrayof claim 45, wherein the gate oxide acts as a tunneling oxide.
 48. Theprogrammable logic array of claim 45, wherein the implemented logicalfunction includes at least one NOR-NOR, AND-OR, OR-AND, NAND-NAND,NOR-OR, OR-NOR, AND-NOR, and NAND-AND.
 49. The programmable logic arrayof claim 45, wherein the first logic plane includes inverters that areadapted to generate complements of the input signals.
 50. Theprogrammable logic array of claim 45, wherein the electrical contactincludes a polysilicon plug.
 51. The programmable logic array of claim45, wherein the stacked capacitor includes a fin type capacitor.
 52. Theprogrammable logic array of claim 45, wherein the stacked capacitorincludes a storage node, a capacitor dielectric, and a plate conductorand wherein the electrical contact couples the storage node of thestacked capacitor to the gate of the transistor.
 53. A programmablelogic array, comprising: a first logic plane that receives a number ofinput signals, the first logic plane having a plurality of non-volatilememory cells arranged in rows and columns that are interconnected toprovide a number of logical outputs; and a second logic plane having anumber of non-volatile memory cells arranged in rows and columns thatreceive the outputs of the first logic plane and that are interconnectedto produce a number of logical outputs such that the programmable logicarray implements a logical function, wherein the non-volatile memorycells each include: a metal oxide semiconductor field effect transistor;a stacked capacitor formed according to a dynamic random access memoryprocess, the capacitor providing a coupling ratio greater than 1.0, thecapacitor including a bottom plate and a top plate separated by acapacitor dielectric; and an electrical contact that couples the bottomplate of the stacked capacitor to a gate of the transistor.
 54. Theprogrammable logic array of claim 53, wherein the bottom plate serves asa storage node.
 55. The programmable logic array of claim 53, whereinthe bottom plate comprises a floating gate for the at least onenon-volatile memory cell.
 56. The programmable logic array of claim 53,wherein the implemented logical function includes at least one ofNOR-NOR, AND-OR, OR-AND, NAND-NAND, NOR-OR, OR-NOR, AND-NOR, andNAND-AND.
 57. The programmable logic array of claim 53, wherein thefirst logic plane includes inverters that generate complements of theinput signals.
 58. The programmable logic array of claim 53, wherein theelectrical contact includes a polysilicon plug.
 59. The programmablelogic array of claim 53, wherein the stacked capacitor includes a fintype capacitor.
 60. A programmable logic array, comprising: a firstlogic plane that receives a number of input signals, the first logicplane having a plurality of non-volatile memory cells arranged in rowsand columns that are interconnected to provide a number of logicaloutputs; and a second logic plane having a number of non-volatile memorycells arranged in rows and columns that receive the outputs of the firstlogic plane and that are interconnected to produce a number of logicaloutputs such that the programmable logic array implements a logicalfunction, wherein the non-volatile memory cells each include: a metaloxide semiconductor field effect transistor; a cup-shaped stackedcapacitor formed according to a dynamic random access memory process,the capacitor providing a coupling ratio greater than 1.0, the capacitorincluding a bottom plate and a top plate separated by a capacitordielectric; and an electrical contact that couples the bottom plate ofthe stacked capacitor to a gate of the transistor.
 61. The programmablelogic array of claim 60, wherein the bottom plate serves as a storagenode.
 62. The programmable logic array of claim 60, wherein the bottomplate comprises a floating gate for the at least one non-volatile memorycell.
 63. The programmable logic array of claim 60, wherein theimplemented logical function includes at least one of NOR-NOR, AND-OR,OR-AND, NAND-NAND, NOR-OR, OR-NOR, AND-NOR, and NAND-AND.
 64. Theprogrammable logic array of claim 60, wherein the first logic planeincludes inverters that are adapted to generate complements of the inputsignals.
 65. The programmable logic array of claim 60, wherein theelectrical contact includes a polysilicon plug.
 66. A programmable logicarray, comprising: a first logic plane that receives a number of inputsignals, the first logic plane having a plurality of non-volatile memorycells arranged in rows and columns that are interconnected to provide anumber of logical outputs; and a second logic plane having a number ofnon-volatile memory cells arranged in rows and columns that receive theoutputs of the first logic plane and that are interconnected to producea number of logical outputs such that the programmable logic arrayimplements a logical function, wherein the non-volatile memory cellseach include: a metal oxide semiconductor field effect transistorcomprising a gate and a channel region separated by a gate oxide; acup-shaped stacked capacitor formed according to a dynamic random accessmemory process, the capacitor providing a coupling ratio greater than1.0; and an electrical contact that couples the stacked capacitor to agate of the transistor.
 67. The programmable logic array of claim 66,wherein the gate oxide acts as a tunneling oxide.
 68. The programmablelogic array of claim 66, wherein the implemented logical functionincludes at least one of NOR-NOR, AND-OR, OR-AND, NAND-NAND, NOR-OR,OR-NOR, AND-NOR, and NAND-AND.
 69. The programmable logic array of claim66, wherein the first logic plane includes inverters that are adapted togenerate complements of the input signals.
 70. The programmable logicarray of claim 66, wherein the electrical contact includes a polysiliconplug.
 71. The programmable logic array of claim 66, wherein the stackedcapacitor includes a storage node, a capacitor dielectric, and a plateconductor and wherein the electrical contact couples the storage node ofthe stacked capacitor to the gate of the transistor.
 72. A programmablelogic array, comprising: a first logic plane that receives a number ofinput signals, the first logic plane having a plurality of non-volatilememory cells arranged in rows and columns that are interconnected toprovide a number of logical outputs; and a second logic plane having anumber of non-volatile memory cells arranged in rows and columns thatreceive the outputs of the first logic plane and that are interconnectedto produce a number of logical outputs such that the programmable logicarray implements a logical function, wherein the non-volatile memorycells each include: a metal oxide semiconductor field effect transistorcomprising a gate and a channel region separated by a gate oxide, thegate oxide being adapted to act as a tunneling oxide; a capacitor formedaccording to a dynamic random access memory process, the capacitorproviding a coupling ratio greater than 1.0; and an electrical contactthat couples the stacked capacitor to a gate of the transistor.